1. Field of the Invention
The present invention relates to a multiplexer, and in particular, to a multiplexer that produces multi-level output signals.
2. Discussion of the Related Art
A multiplexer is a logic circuit for selecting a signal from a plurality of input signals and producing the selected input signal as a single output signal. Selection of the output signal is accomplished by a selection signal, which is another input signal. Such multiplexers are useful in semiconductor circuits. Usually, operational characteristics of the multiplexer are understood as used in a digital logic circuit. In addition, the multiplexer can be used for analog signals or if digital signals and the analog signals are treated together.
The multiplexer having such a wide application has a very important position in a Liquid Crystal Display driving circuit (LCD driving circuit). The LCD driving circuit is a circuit for supplying picture signals to each pixel of LCD panels. In the LCD panels, a plurality of LCD cells forming the pixels are arranged in a matrix structure and are operated by picture signals transmitted through MOS transistors, which are switching elements. The LCD driving circuit is a circuit for providing proper picture signals to each of the MOS transistors.
Methods for driving a LCD include a dot inverting method, a column inverting method, a line inverting method, etc. and are implemented by inverting LCD panels in a unit of dot, column and line, respectively. Reasons for using such a variety of inverting methods is to prevent degradation of the LCD by supplying serial voltage, or to prevent flickers that occur when pixel voltage is varied in every fields or to prevent after images appearing when a still scene is provided for a long time.
To implement a method for inverting the LCD panels, polarities of the signals provided to each of the pixels of the LCD panels are alternatively inverted. That is, the polarities of the input signals are alternatively inverted to a positive (+) polarity and a negative (-) polarity centering around a common voltage (e.g., Vcom.)
The multiplexer as described above is used to alternatively invert the polarity of the input signal. A high voltage signal from a circuit for producing a high voltage and a low voltage signal from a circuit for producing a low voltage with reference to the common voltage is selectively taken using the multiplexer. Thus, the multiplexer receives both of the high voltage level signal and the low voltage level signal.
FIG. 1 is a prior art circuit of a transmission gate having a two-level output signal. As shown in FIG. 1, an input signal having 0V or 10V is transferred through the NMOS transistor logic or the PMOS transistor logic. The output path is controlled by an output enable signal EN or an output enable bar signal ENB, which are alternative signals of 0V or 10V.
Since the transmission gate of FIG. 1 is a circuit for obtaining a high voltage output signal through a standard or typical CMOS process, the supplying voltage of each of the MOS transistors is about 5V rated voltage. Thus, since a peak value of the input voltage, 10V can not be accepted, a shield voltage VSHLD is used to prevent the elements from being broken down. The shield voltage VSHLD is set to half of the input voltage, 5V.
When a signal of 5 to 10V is provided to an input stage IN of FIG. 1, an NMOS transistor Q1 is turned off. Accordingly, an output is not produced through the NMOS transistor logic. However, a PMOS transistor Q2 is turned on and provides a 5 to 10V voltage to a source of a PMOS transistor Q6. In this state, if the output enable bar signal ENB goes to 0V, the PMOS transistor Q6 is also turned on to produce the voltage of 5 to 10V, which was transferred from the PMOS transistor Q2. A PMOS transistor Q8 is also turned on in the same manner as the PMOS transistor Q2 to produce the voltage of 5 to 10V at the output stage OUT.
On the contrary, when the signal of 0 to 5V is provided to the input stage IN, the PMOS transistor Q2 is turned off. Accordingly, an output is not produced through the PMOS transistor logic. At this time, the NMOS transistor Q1 is turned on to provide the voltage of 0 to 5V to a drain of an NMOS transistor Q4. In this state, when the output enable signal EN goes to 10V, an NMOS transistor Q3 is turned on. The 10V voltage is provided to a gate of the NMOS transistor Q4, and then the NMOS transistor Q4 is also turned on. An NMOS transistor Q7 is also turned on in the same manner as the NMOS transistor Q1 to produce the voltage of 0 to 5V at the output stage OUT.
However, since in the transmission gate of FIG. 1, the range of the signal level for controlling the output path should be the same voltage level as the peak value of the input signal, it is difficult or impossible that the output voltage fully swings in the same voltage range as the input voltage range. In addition, elements connected to the output stage may be broken down by the high or the low output voltage. That is, in the transistor logic of the NMOS transistor logic and the PMOS transistor logic through which the output voltage does not pass, the transistor connected to the output stage (e.g., NMOS transistor Q7 or PMOS transistor Q8) can be broken down by the low or high output voltage.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.